A Physically-addressed L4 Kernel

All current implementations of the L4 microkernel map thread control blocks (TCBs) into a linear array in virtual memory, a decision that was originally made almost entirely for the performance advantages it offers on the Intel 486 platform. The drawback of this design choice is that page faults generated within L4 complicate the kernel and in particular its verification by formal methods. An alternative exists however on architectures where physical addressing, or at least a loose equivalent in superpages, is available. On such architectures, TCBs may be addressed physically via indirection provided by an auxiliary lookup table. Addressing TCBs in this manners leads to a completely physically-addressed L4 kernel that offers advantages in simplicity, but has a non-obvious effect on the cache footprint of the performancecritical IPC path that warrants examination. This thesis endeavours to provide a thorough investigation into the performance trade-offs involved in making the L4Ka::Pistachio implementation of the L4 Version 4 API completely physically addressed. We stress architectural issues that effect the outcome of these trade-offs and explore various implementational design choices that aim to weaken the performance penalties a physically-addressed kernel may suffer. We conclude by running Linux on top of the L4 microkernel to obtain a concise set of benchmarks that prove, at least for the MIPS64 architecture, that the simplicity of a completely physically-addressed L4 kernel may be enjoyed without any notable performance degradation.